نکته :
علاوه بر اجزای گفته شده ، ممکن است برخی قسمت های داخلی نیز برای FPGA تعبیه شده باشد ، نظیر ALU و ... که بستگی به طراحی شرکت سازنده دارد .
کاربرد FPGA :
برنامه نویسی و طراحی با FPGA :
- با استفاده از زبان های توصیف سخت افزاری مانند VHDL ، AHDL ، HDL و ...
- با استفاده از طراحی مدار
به طور کلی استفاده از زبان VHDL به دلیل استاندارد بودن آن ، کاربرد بیشتری در طراحی مدارات دارد . برای اطلاعات بیشتر در مورد VHDL به لینک زیر مراجعه کنید :
کتاب آموزشی :
در لینک زیر نیز یک کتاب آموزشی مناسب برای یادگیری FPGA معرفی شده است :
مقالات آموزشی مفید:
http://up.iranblog.com/37261/1265960052.pdf
up.iranblog.com/37261/1266007321.pdf
up.iranblog.com/37261/1266020544.pdf
up.iranblog.com/37261/1266004068.pdf
up.iranblog.com/37261/1266006573.pdf
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Port ( clk : in STD_LOGIC;
data : out STD_LOGIC_VECTOR (3 downto 0));
end estepmotor;
data <= "1000" when mari = "0000" else
"1100" when mari = "0001" else
"0100" when mari = "0010" else
"0110" when mari = "0011" else
"0010" when mari = "0100" else
"0011" when mari = "0101" else
"0001" when mari = "0110" else
"1001" when mari = "0111";
begin
then
mari <= mari + '1';
if mari >= x"7" then
mari <= x"0";
end if;
end if;
end process;
LCD 2*16برنامه
--{ FileName............: Lcd_controller_main.vhd
--{ Project.............: FPGA
--{------------------------------------------------------------------------------}
--{
--{ Notes: has some design flaws
--{
--{
--{ Physical 'Testbench' for LCD_CONTROLLER
--{ Output signals on prototyping board:
--{ J4-6 260 ns cycle signal
--{ J4-8 1 ms cycle signal (1 kHz)
--{ J4-10 0.2 ms cycle signal (5 kHz)
--{------------------------------------------------------------------------------}
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--{------------------------------------------------------------------------------}
--{ Xilinx primitives libraries used
--{------------------------------------------------------------------------------}
library UNISIM;
use UNISIM.VComponents.all;
entity LCD_CONTROLLER_MAIN is
port(
CLK_SMT : in std_logic;
PUSH_RESET: in std_logic;
PUSH : in std_logic_vector(2 downto 1);
LCD_DB : out std_logic_vector (7 downto 0);
LCD_E : out std_logic;
LCD_RS : out std_logic;
PIEZO : out std_logic;
P1_LIO_A09: out std_logic;
P1_LIO_A13: out std_logic;
P1_LIO_A15: out std_logic
);
end LCD_CONTROLLER_MAIN;
--{------------------------------------------------------------------------------}
--{ Architecture
--{------------------------------------------------------------------------------}
architecture LCD_CONTROLLER of LCD_CONTROLLER_MAIN is
component CLOCK_DIV is
generic(
CLK_TIMING_IN_NS : natural; -- Input clock cycle time (in ns)
CLK_TIMING_OUT_NS: natural -- Input clock cycle time (in ns)
);
port(
CLK_IN : in std_logic; -- Input clock
CLK_OUT: out std_logic -- Output clock
);
end component;
component LCD_CONTROLLER is
port(
RST : in std_logic; -- Reset
CLK : in std_logic; -- Clock (>= 250 ns cycle time)
START : in std_logic; -- Start flag
RS : in std_logic; -- Register select
DATA : in std_logic_vector (7 downto 0); -- Data
E_PORT : out std_logic; -- Enable signal port
RS_PORT : out std_logic; -- Register select port
DATA_PORT : out std_logic_vector (7 downto 0); -- Data port
READY : out std_logic -- Ready flag
);
end component;
type tstate_main is (wait1, init1, init2, text1, text2, crlf1, crlf2, text3, text4, idle,
crlf3, crlf4, press1, press2, press3, crlf5, crlf6, press4, press5, press6);
type ttextlength is range 16 downto 0;
type tline is array(ttextlength) of std_logic_vector (7 downto 0);
type tinitlength is range 8 downto 0;
type tinitdata is array(tinitlength) of std_logic_vector (7 downto 0);
constant init_data : tinitdata := (x"38", x"38", x"38", x"38", x"06", x"0E", x"01", x"80", x"00");
constant line1 : tline := (x"20", x"20", x"20", x"20", x"20", x"4C", x"49", x"53",
x"4D", x"41", x"52", x"20", x"20", x"20", x"20", x"20", x"00");
constant line2 : tline := (x"45", x"6E", x"67", x"69", x"6E", x"65", x"65", x"72",
x"69", x"6E", x"67", x"20", x"42", x"2E", x"56", x"2E", x"00");
constant line3 : tline := (x"42", x"75", x"74", x"74", x"6F", x"6E", x"20", x"31",
x"20", x"70", x"72", x"65", x"73", x"73", x"65", x"64", x"00");
constant line4 : tline := (x"42", x"75", x"74", x"74", x"6F", x"6E", x"20", x"32",
x"20", x"70", x"72", x"65", x"73", x"73", x"65", x"64", x"00");
signal state : tstate_main; -- Current state main state amchine
signal text_index : ttextlength; -- Index counter
signal init_index : tinitlength; -- Index counter
signal clk : std_logic; -- Buffered master clock
signal rst : std_logic; -- Reset signal
signal start : std_logic; -- Start flag for writing to LCD
signal ready : std_logic; -- Ready flag (ready for writing to LCD)
signal rs : std_logic; -- RS data for LCD
signal data : std_logic_vector (7 downto 0); -- Data to write to LCD
signal clk_out : std_logic; -- LCD clock
signal clk_1ms : std_logic; -- Timing signal (piezo)
signal clk_02ms: std_logic; -- Timing signal (piezo)
signal push1_p : std_logic_vector (3 downto 0); -- Debouncing PUSH1 button
signal push1_d : std_logic; -- Debounced PUSH1 button
signal push2_p : std_logic_vector (3 downto 0); -- Debouncing PUSH2 button
signal push2_d : std_logic; -- Debounced PUSH2 button
begin
CLK_250NS_I : CLOCK_DIV
generic map (
CLK_TIMING_IN_NS => 13,
CLK_TIMING_OUT_NS => 260
)
port map (
CLK_IN => clk,
CLK_OUT => clk_out
)
;
CLK_1MS_I : CLOCK_DIV
generic map (
CLK_TIMING_IN_NS => 13,
CLK_TIMING_OUT_NS => 1000000
)
port map (
CLK_IN => clk,
CLK_OUT => clk_1ms
)
;
CLK_02MS_I : CLOCK_DIV
generic map (
CLK_TIMING_IN_NS => 13,
CLK_TIMING_OUT_NS => 200000
)
port map (
CLK_IN => clk,
CLK_OUT => clk_02ms
)
;
UUT : LCD_CONTROLLER
port map (
RST => rst,
CLK => clk_out,
START => start,
RS => rs,
DATA => data,
E_PORT => LCD_E,
RS_PORT => LCD_RS,
DATA_PORT => LCD_DB,
READY => ready
)
;
--{------------------------------------------------------------------------------}
--{ Descript: Clock buffering
--{------------------------------------------------------------------------------}
BUFGDLL_INST1: BUFGDLL
port map (
I => CLK_SMT,
O => clk
)
;
--{------------------------------------------------------------------------------}
--{ Params : Clock
--{ Descript: Debounce the input. This is done by checking the
--{ input for a number of cycles and when all of them are
--{ equal the output changes.
--{------------------------------------------------------------------------------}
process (clk_1ms)
begin
if (rising_edge(clk_1ms)) then
push1_p(0) <= not(PUSH(1));
push1_p(1) <= push1_p(0);
push1_p(2) <= push1_p(1);
push1_p(3) <= push1_p(2);
if (push1_p = "1111") then
push1_d <= '1';
else
if (push1_p = "0000") then
push1_d <= '0';
end if;
end if;
end if;
end process;
process (clk_1ms)
begin
if (rising_edge(clk_1ms)) then
push2_p(0) <= not(PUSH(2));
push2_p(1) <= push2_p(0);
push2_p(2) <= push2_p(1);
push2_p(3) <= push2_p(2);
if (push2_p = "1111") then
push2_d <= '1';
else
if (push2_p = "0000") then
push2_d <= '0';
end if;
end if;
end if;
end process;
--{------------------------------------------------------------------------------}
--{ Main state machine
--{------------------------------------------------------------------------------}
--{------------------------------------------------------------------------------}
--{ Params : Clock
--{ Reset
--{ Descript: Main state machine: State register
--{------------------------------------------------------------------------------}
process (clk, rst)
begin
if (rst = '1') then
start <= '0';
state <= wait1;
else
if (rising_edge(clk)) then
case state is
when wait1 => start <= '0'; -- Make sure LCD sequence stops
state <= init1;
init_index <= tinitlength'HIGH;
when init1 => if (ready = '1') then -- Wait for LCD ready to accept command
data <= init_data(init_index);
init_index <= init_index - 1;
start <= '1'; -- Start LCD sequence
rs <= '0';
state <= init2;
end if;
when init2 => if (ready = '0') then -- Wait for LCD sequence started
start <= '0'; -- Make sure sequence not automatically restarted
if (init_index = 0) then -- Did we just send the last initialization data?
state <= text1;
text_index <= ttextlength'HIGH;
else
state <= init1;
end if;
end if;
when text1 => if (ready = '1') then -- Wait for LCD ready to accept command
data <= line1(text_index);
text_index <= text_index - 1;
start <= '1'; -- Start LCD sequence
rs <= '1';
state <= text2;
end if;
when text2 => if (ready = '0') then -- Wait for LCD sequence started
start <= '0'; -- Make sure sequence not automatically restarted
if (text_index = 0) then -- Did we just send the last text line 1 data?
state <= crlf1;
else
state <= text1;
end if;
end if;
when crlf1 => if (ready = '1') then -- Wait for LCD ready to accept command
data <= x"C0"; -- DDRAM Address set: address $40 (2nd line)
start <= '1'; -- Start LCD sequence
rs <= '0';
state <= crlf2;
end if;
when crlf2 => if (ready = '0') then -- Wait for LCD sequence started
start <= '0'; -- Make sure sequence not automatically restarted
state <= text3;
text_index <= ttextlength'HIGH;
end if;
when text3 => if (ready = '1') then -- Wait for LCD ready to accept command
data <= line2(text_index);
text_index <= text_index - 1;
start <= '1'; -- Start LCD sequence
rs <= '1';
state <= text4;
end if;
when text4 => if (ready = '0') then -- Wait for LCD sequence started
start <= '0'; -- Make sure sequence not automatically restarted
if (text_index = 0) then -- Did we just send the last text line 2 data?
state <= idle;
else
state <= text3;
end if;
end if;
when idle => if (push1_d = '1') then
state <= crlf3;
else
if (push2_d = '1') then
state <= crlf5;
else
state <= idle;
end if;
end if;
when crlf3 => if (ready = '1') then -- Wait for LCD ready to accept command
data <= x"80"; -- DDRAM Address set: address $00 (1st line)
start <= '1'; -- Start LCD sequence
rs <= '0';
state <= crlf4;
end if;
when crlf4 => if (ready = '0') then -- Wait for LCD sequence started
start <= '0'; -- Make sure sequence not automatically restarted
state <= press1;
text_index <= ttextlength'HIGH;
end if;
when press1 => if (ready = '1') then -- Wait for LCD ready to accept command
data <= line3(text_index);
text_index <= text_index - 1;
start <= '1'; -- Start LCD sequence
rs <= '1';
state <= press2;
end if;
when press2 => if (ready = '0') then -- Wait for LCD sequence started
start <= '0'; -- Make sure sequence not automatically restarted
if (text_index = 0) then -- Did we just send the last text line 1 data?
state <= press3;
else
state <= press1;
end if;
end if;
when press3 => if (push1_d = '1') then
state <= press3;
else
state <= wait1;
end if;
when crlf5 => if (ready = '1') then -- Wait for LCD ready to accept command
data <= x"80"; -- DDRAM Address set: address $00 (1st line)
start <= '1'; -- Start LCD sequence
rs <= '0';
state <= crlf6;
end if;
when crlf6 => if (ready = '0') then -- Wait for LCD sequence started
start <= '0'; -- Make sure sequence not automatically restarted
state <= press4;
text_index <= ttextlength'HIGH;
end if;
when press4 => if (ready = '1') then -- Wait for LCD ready to accept command
data <= line4(text_index);
text_index <= text_index - 1;
start <= '1'; -- Start LCD sequence
rs <= '1';
state <= press5;
end if;
when press5 => if (ready = '0') then -- Wait for LCD sequence started
start <= '0'; -- Make sure sequence not automatically restarted
if (text_index = 0) then -- Did we just send the last text line 1 data?
state <= press6;
else
state <= press4;
end if;
end if;
when press6 => if (push2_d = '1') then
state <= press6;
else
state <= wait1;
end if;
when others => state <= wait1;
end case;
end if;
end if;
end process;
rst <= not PUSH_RESET;
P1_LIO_A09 <= clk_out;
P1_LIO_A13 <= clk_1ms;
P1_LIO_A15 <= clk_02ms;
PIEZO <= (clk_1ms and push1_d) or (clk_02ms and push2_d);
end LCD_CONTROLLER;
KPD برنامه
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:32:37 08/31/07
-- Design Name:
-- Module Name: keyboard - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity keyboard is
Port ( KB_ROW : buffer std_logic_vector(3 downto 0);
KB_COL : in std_logic_vector(3 downto 0);
KB_CLK : in std_logic;
KB_RST : in std_logic;
KB_VAL : out std_logic_vector(7 downto 0);
KB_VLD : out std_logic;
KB_BLL : out std_logic);
end keyboard;
architecture Behavioral of keyboard is
constant MAXSCAN1: std_logic_vector(3 downto 0):= X"4";
constant BELLDIV : std_logic_vector(4 downto 0):= "11111";
signal SCANTMP :std_logic_vector(7 downto 0);
signal SCANVAL :std_logic_vector(7 downto 0);
signal SCANCNT :std_logic_vector(3 downto 0);
signal BL_CNT :std_logic_vector(4 downto 0);
signal BL_FRQ :std_logic;
signal BL_ENA :std_logic;
begin
KB_BLL <= not(KB_CLK and BL_ENA);
process(KB_CLK,KB_RST)
begin
if(KB_RST = '0') then
SCANVAL <= X"FF";
SCANCNT <= MAXSCAN1;
BL_ENA <= '0';
KB_VAL <= X"FF";
KB_ROW <= X"E";
KB_VLD <= '0';
elsif(KB_CLK'event and KB_CLK = '1') then
case KB_ROW is
when X"E" => KB_ROW <= X"D";
when X"D" => KB_ROW <= X"B";
when X"B" => KB_ROW <= X"7";
when X"7" => KB_ROW <= X"F";
when X"F" => KB_ROW <= X"E";
when others=>KB_ROW <= X"E";
end case;
if(KB_ROW = X"F") then
SCANTMP <= X"FF";
if(SCANTMP = X"FF" or SCANTMP /= SCANVAL) then
SCANVAL <= SCANTMP;
SCANCNT <= MAXSCAN1;
BL_ENA <= '0';
KB_VLD <= '0';
else
if(SCANCNT > X"1") then
SCANCNT <= SCANCNT-1;
BL_ENA <= '1';
KB_VLD <= '0';
elsif(SCANCNT = X"1") then
case SCANVAL is
when X"EE" => KB_VAL<=X"55";
when X"ED" => KB_VAL<=X"44";
when X"EB" => KB_VAL<=X"42";
when X"E7" => KB_VAL<=X"45";
when X"DE" => KB_VAL<=X"39";
when X"DD" => KB_VAL<=X"36";
when X"DB" => KB_VAL<=X"33";
when X"D7" => KB_VAL<=X"52";
when X"BE" => KB_VAL<=X"38";
when X"BD" => KB_VAL<=X"35";
when X"BB" => KB_VAL<=X"32";
when X"B7" => KB_VAL<=X"2E";
when X"7E" => KB_VAL<=X"37";
when X"7D" => KB_VAL<=X"34";
when X"7B" => KB_VAL<=X"31";
when X"77" => KB_VAL<=X"30";
when others => KB_VAL<=X"67";
end case;
SCANCNT <= X"0";
KB_VLD <= '1';
else
KB_VLD <= '0';
end if;
end if;
elsif(KB_COL /= X"F") then SCANTMP(3 downto 0)<=KB_ROW; SCANTMP(7 downto 4)<=KB_COL;
else SCANTMP <= SCANTMP;
end if;
end if;
end process;
end Behavioral;
----------------------------------------------------------------------------
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Port ( clk : in STD_LOGIC;
segment : out STD_LOGIC_vector (3 downto 0);
output : out bit_vector (6 downto 0));
end segm;
type x is array (9 downto 0) of bit_vector (6 downto 0);
signal a:x:=("1111110","0110000","1101101","1111001","0110011","1011011","1011111","1110000","1111111","1111011");
signal cant : std_logic_vector (1 downto 0);
signal y,d,s,h : integer range 0 downto 9 ;
begin
a(d) when cant = "01" else
a(s) when cant = "01" else
a(h) when cant = "01";
segment <= "0001" when cant = "00" else
"0010" when cant = "01" else
"0100" when cant = "10" else
"1000" when cant = "11";
process (clk)
begin
if rising_edge(clk)
then
cant <= cant + 1;
y <= 1;
d <= 2;
s <= 3;
h <= 4;
end if;
end Behavioral;
